Predator
Description
The Predator SDR is a massive all-in-one radio that leverages the latest in Analog Devices’ RF technology and AMD field-programmable gate array (FPGA) processing capabilities. The ADRV9026 paired with an XCZU11EG provide ample onboard processing capabilities while the many digital inputs/outputs (I/Os) allow offloading data for host-side processing.
Documentation
For additional information, download the Predator Product Brief
Order
PRD-01
Orders may be placed via e-mail, telephone, fax, or mail.
Commercial Price List available upon request.
E-mail: sales@rincon.com
Phone: 520-519-3131
Fax: 520-519-3120
Mail: Rincon Research Corporation
Attention: Sales
101 North Wilmot Road, Suite 101
Tucson, AZ 85711
WARNING: Commodities, including associated software, firmware, and technical data, offered for sale on this site are controlled for export by the U.S. Department of State under the International Traffic in Arms Regulations (ITAR) or by the Department of Commerce under the Export Administration Regulations (EAR). Purchaser is required by U.S. law to comply with these regulations. Export, re-export, and retransfer of these commodities by any means without the required licenses or other U.S. Government authorization is prohibited by U.S. law.
Technical Specifications
FPGA XCZU11EG-1FFVC1156E
4-GB RAM FPGA processor (PS)
4-GB RAM FPGA programmable logic (PL)
RF Transceiver ADRV9026
75 MHz to 6 GHz RX and TX
245.76-Msps maximum sample rate
Up to 200 MHz instantaneous bandwidth
Two independent tuners
4 RX channels — 2 SMPM RX with preselect filter, gain, attenuation; 2 RX channels over differential cable via ARF
4 TX channels — 2 SMPM TX with preselect filters; 2 TX channels over differential cable via ARF
JESD204c Digital Interface
Command and control
1 GbE RJ45
10 GbE
Cabled to external 4x SFP interface
Samtec ARF6-RA Slim Socket for ARC6
PCIe Gen3x4
Samtec Razor Beam™ LSHM high-speed terminal/socket strip
Either host or endpoint configurable
Expansion connector
20-pin Pico-Clasp header
8 GPIO (differential pair capable pins)
Dedicated I2C bus for external board control
SFP management controls for 10 GbE
Logic-level UART connection for GPS-NMEA messages
Fractional-N reference clock
Configurable external reference frequency
Internal reference operation
SMPM 50 Ω connector
1PPS
SMPM 50 Ω connector
FPGA JTAG, processor UART console
USB 2.0, Type-C connector
SWaP
Dimensions — 106 mm x 80 mm (4.2” x 3.15”)
Weight — 3 oz. (est)
Power — 70 Watts peak
Power supply
9–16VDC
50 A core supply