The DSPBrik™ DE4002 Input Module produces up to four channels of Differential ECL data up to 100 mega-samples-per-second (MSPS).

 

 
 

DSPBrik™ 4-CH Differential ECL Input Module DE4002

 
 

Features

  • Four independent Differential ECL (DECL) Input Channels
  • 16 data bits + clock (differential pairs)
  • Factory/User customizable data formatting FPGA
 

Description

Rincon's Model DE4002 DSPBrik™ converts up to four 16-bit Differential ECL (DECL) input channels via the four SCSI+ .050 50-pin connectors into the standard DSPBrik™ I/O connector format for output via the high speed edge connector. Each input channel receives an independent data clock which is used to register data on the falling edge of the clock to account for skew in the differential cabling. Data rates approaching 100 million samples per second per channel are possible.

 

Specifications

 

General:

 FPGA Size 0.5 Million Gates
 Power Connector Molex 3-pin Mini-Fit JR
 

Input:

 Connectors 4
 Data 16-bit Differential
 Clock One Differential Pair per Channel
 Data Rate 100 MSPS (max.)
 Signal Level Negative Differential ECL (DECL)
 Style SCSI+ .050 50 Pin Connector
 

Output:

 Edge Connector(s) 1
 Number of Ports 4 per edge connector
 Data 16-bit (single ended)
 Clock 1 LVDS pair per port
 Data Rate 100 MSPS (max.)
 Signal Level LVCMOS
 Style QSH-090
 

Physical Properties:

 Dimensions 3-7/8"W X 3-7/8"H X 1-3/4"D, Edge connectors add 3/16-inch to height and width
 Temperature, Operating 0-70C
 Power 10-13 VDC